1. Field of Invention
The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, and more particularly to an improved Complementary Metal Oxide Semiconductor (CMOS) device with a lower external resistance and a method for fabricating the improved CMOS device.
2. Description of the Prior Art
An important property of high performance semiconductor devices is the ability to conduct electricity. Current is inversely related to resistance. Traditionally, increasing the cross-section of the semiconducting material; shortening the length for the electron path; increasing the voltage; or decreasing the resistivity of the semiconducting material can all decrease resistivity and increase electron flow through electrical devices.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide, semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device must be scaled simultaneously in order to optimize electrical performance of a device.
One of the primary challenges to MOSFET scaling is lowering the device's external resistance (Rext), also known as source/drain resistance. External resistance is the sum of all of the resistance values in a MOSFET device except for channel resistance. The external resistance is attributed to doping and diffusion of the wafer as well as the silicidation process. When scaling MOSFET devices, and if the device gate-length and the gate oxide thickness are reduced and the external resistance is held constant, then the performance benefits achieved through scaling will be limited.
In conventional MOSFET designs, as depicted in FIG. 1, a gate region 5 is formed atop a Si-containing substrate 10. The gate region 5 includes a gate silicide 4 atop a gate conductor 3, which is positioned atop a gate dielectric 2. The Si-containing substrate 10 includes deep source/drain regions 6, source/drain extensions 7, thick silicide contacts 8, and a channel region 9. The source/drain extensions 7 partially extend under the gate region 5. The electron path W1, through which the current of electron flow to reach the silicide region 8 begins at the end of the source/drain extensions 7 abutting the channel region 9 and extends to the thick silicide region 8. Decreasing the dimensions of the electron path W1 increases the performance of the device. Therefore, it would be desirable to decrease the electron path W1 by decreasing the distance between the silicide region and the end of the source/drain extension regions 7 abutting the channel region 9.
Utilizing current MOSFET designs, the electron path W1, i.e., path of current through the source/drain extension region 7 prior to reaching the low-resistance thick silicide 8, is on the order of 60 nm. In conventional MOSFET designs, the thick silicide 8 cannot be brought closer to the channel for the following reasons:
First, conventional MOSFET designs utilize thick silicide layers for reducing the sheet resistance between the devices incorporated in the chip's design. The thicker the silicide, the greater the cross-section of the interconnect, resulting in a low resistance/high current interconnect. Thick silicides form into the substrate in both horizontal and vertical directions during anneal processing steps and therefore must have appropriate spacing away from the extension edge at the channel-end tip and the extension edge at the bottom of the junction.
For example, when utilizing cobalt for silicidation, a 5–10 nm deposited Co layer will diffuse to a depth of approximately 20–40 nm and will also diffuse laterally. Thick silicide regions can give rise to a substantial degree of interface roughness, which can lead to punch-through of the thin extension junctions. Punch-through can lead to excessive level of junction leakage. The above limit on how close a silicide may be brought to the channel without statistical failure or penalty in yield is a fundamental integration constraint for the conventional MOSFET.
Second, in order to bring the silicide closer to the channel region 9, the final spacer width must be reduced, decreasing the distance between the deep source/drain regions 6 and the channel region 9. Decreasing the proximity between the deep source/drain regions 6 and the channel region 9 increases the interaction between the deep source/drain regions 6 and the channel region 9 resulting in increased short channel effects. Short channel effects are well known to those skilled in the art as a decrease in threshold voltage, Vt, due to electrical charge sharing between the gate and the source drain regions, resulting in degradation of the devices ability to control whether the device is on or off.
It would be desirable to provide a MOSFET device that has a minimized external resistance.